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Lattice Semiconductor
10Gb Ethernet XGXS IP Core User’s Guide
Additional pinout speci ? cation information may be found in the XGXS core ORCA PAD speci ? cation ? les included
with this IP.
I/O Timing and Electrical Speci ? cations
XGMII Speci ? cations
Clause 46 of IEEE 802.3ae speci ? es HSTL1 I/O with a 1.5V output buffer supply voltage for all XGMII signals. The
HSTL1 speci ? cations comply with EIA/JEDEC Standard EIA/JESD8-6 using Class I output buffers with output
impedance greater than 38 ? to ensure acceptable overshoot and undershoot performance in an unterminated
interconnection. The parametric values for HSTL XGMII signals are given in Table 15. The HSTL termination
scheme is shown in Figure 12. Timing requirements for chip-to-chip XGMII signals are shown in Figure 13.
Additional information on XGMII interface speci ? cations may be found in IEEE 802.3ae. Additional information on
implementing the XGMII DDR capabilities in the ORT82G5 may be found in Lattice technical notes TN1036 ORCA
Series 4 I/O User’s Guide and TN1037 ORCA Series 4 Fast DDR Interface.
Table 15. XGMII DC and AC Speci?cations
Parameter
VDDIO
VREF
VTT 1
VIH
VIL
VOH 2
VOL
Condition
—
—
—
—
—
IOH > 8mA
IOL > -8mA
Min.
1.4
0.68
-
V REF + 100mV
-0.3
1
—
Typ.
1.5
0.75
0.75
0.85
0.65
1.1
—
Max.
1.8
0.9
-
V DDIO + 0.3
V REF - 100mV
—
0.4
Units
V
V
V
V
V
V
V
1. 50% V DDIO
2. V DDIO - 400mV
Figure 12. HSTL1 Circuit Topology
V DD IO = 1.5V
Z = 50
V TT = 0.75V
R = 50 ?
V REF = 0.75V
26
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